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RLDRAM (countable and uncountable, plural RLDRAMs)

  1. (computing) Initialism of reduced latency dynamic random access memory.
    • 2005, J.F. Broenink, H.W. Roebbers, J.P.E. Sunter, Communicating Process Architectures 2005: WoTUG-28, IOS Press, →ISBN, page 344:
      A single 32 MByte RLDRAM and its controller has enough throughput to support many PEs possibly up to 20 if some wait states are accepted. Bank collisions are mostly avoided by the MMU hashing policy. There are several Virtex-II-Pro boards with RLDRAM on board which can clock the RLDRAM at 300 MHz with DDR I/O, well below the 400 MHz specification, but the access latency is still 20 ns or 8 clocks.
    • 2008, Brent Keeth, DRAM Circuit Design: Fundamental and High-Speed Topics, John Wiley & Sons, →ISBN, page 188:
      An example of this is evident in reduced latency DRAMs (RLDRAMs). Figure 8.11 shows a typical Read operation for an RLDRAM. A row activation cycle with Read and Precharge takes less than 15 ns from start to finish, as shown. These devices are built to serve applications that previously resorted to using SRAM. RLDRAMs have a traditional SRAM broadside address interface but are otherwise DRAMs built for low cycle times and low Read latency.
    • 2010, Bruce Jacob, Spencer Ng, David Wang, Memory Systems: Cache, DRAM, Disk, Morgan Kaufmann, →ISBN, page 494:
      The first-generation RLDRAM device was designed by Infineon to meet the demands of the market for networking equipment. Subsequently, Micron was brought in as a partner to co-develop RLDRAM and provide a second source. However, Infineon has since abandoned RLDRAM development, and Micron proceeded ahead to develop the second-generation RLDRAM II. RLDRAM and RLDRAM II were designed for use in embedded applications.